- three HS-LINKs from each DSP are available on the rear side of the
- two LINKs interconnect DSP1 and DSP2
- one LINK per DSP is connected to the FPGA
- all SPORTs are connected to the FPGA
- BootROM (Flash) of DSP1 is programmable via the CompactPCI bus or DSP1
- DSP2 is LINKBooted by DSP1
- Timer-0 is used by Operating Systems
- IRQ-2 (highest priority) signals an interrupt from the IP-Modules to the
DSPs for data communication.
- IRQ-1 (medium priority) signals an interrupt from the CPCI interface
controller PLX9054 to the DSP1 for communication handling.
- IRQ-0 (lowest priority) signals an interrupt from LinkPort failure detection
CPLD, IP-Module or PLX9054 error output to the DSPs for Error handling.
- DSP1/2(Digital Signal Processors)
- PCI controller
- Flash ROM
- IP Mezzanine Module sites
- JTAG Interface